(1) Field of the Invention
The invention relates to arbitration of access to a bus. More specifically, the invention relates to reducing latency in arbitrating bus access.
(2) Related Art
Today's computer systems frequently have multiple devices sharing a bus. Among the possible devices are processors, I/O units, and DMA units. Since only one device can drive the bus at any time, it is necessary to arbitrate between devices requesting the bus to prevent multiple drivers from driving the bus simultaneously and creating invalid transmission packets. Arbitration has typically been performed by arbitration logic which follow the timing scheme shown in FIG. 1. In the first cycle, such prior art arbitration units accept the request along an arbitration bus and in the next cycle, the unit arbitrates between the request received in the previous cycle and grants bus access to the winner. This results in two cycles of latency between an initial request and the winner of the arbitration being granted access to the bus, even if only one device is making a request for bus access.
In view of the fact that the time required for a processor to gain access to the bus becomes a crucial performance bottleneck of currently existing systems, it is desirable, to the extent possible, to eliminate this arbitration latency as it exists in the prior art.